saronix nth / nch series saronix crystal clock oscillator technical data 3.3v, tri-state, hcmos 141 jefferson drive ? menlo park, ca 94025 usa 650-470-7700 800-227-8974 fax 650-462-9894 ds-159 rev b 3.8.1 1 mhz to 70 mhz frequency stability: frequency range: 25, 50 or 100 ppm over all conditions: calibration tolerance, operating temperature, input voltage change, load change, aging, shock and vibration. temperature range: operating: storage: 0 to +70c or -40 to +85c, see part numbering guide -55 to +125c supply voltage: recommended operating: 3.3v 10% supply current: 15ma max 25ma max frequency: 1 to 27 mhz 27+ to 70 mhz actual size description a crystal controlled, low current oscilla- tor providing precise rise and fall times to drive high speed hcmos and nmos microprocessors. the tri-state function on the nth enables the output to go high impedance. device is packaged in a 14 or an 8-pin dip compatible resistance welded, all metal grounded case, to re- duce emi. output drive: symmetry: rise and fall times: logic 0: logic 1: load: jitter: 40/60% or 45/55% max @ 50% v dd, see part numbering guide 4ns max 20% to 80% v dd 10% v dd max 90% v dd min 30 pf 8ps max rms period jitter, 1ps max 1 cycle-to-cycle jitter hcmos mechanical: shock: solderability: terminal strength: vibration: solvent resistance: resistance to soldering heat: mil-std-883, method 2002, condition b mil-std-883, method 2003 mil-std-202, method 211, conditions a & c mil-std-883, method 2007, condition a mil-std-202, method 215 mil-std-202, method 210, condition a, b or c environmental: gross leak test: fine leak test: thermal shock: moisture resistance: mil-std-883, method 1014, condition c mil-std-883, method 1014, condition a2 mil-std-883, method 1011, condition a mil-std-883, method 1004 applications & features clock 16 and 32 bit microprocessors tri-state output on nth hcmos compatible available up to 70 mhz grounded, all metal, full size or half size case plastic smd available, see separate data sheet output waveform t r t f cmos logic 1 80% v dd 50% v dd 20% v dd logic 0 symmetry
saronix nth / nch series saronix crystal clock oscillator technical data 3.3v, tri-state, hcmos 141 jefferson drive ? menlo park, ca 94025 usa 650-470-7700 800-227-8974 fax 650-462-9894 all specifications are subject to change without notice. ds-159 rev b 3.8.2 symmetry 0 = 40/60% max, 0 to 70c a = 45/55% max, 0 to 70c 2 = 40/60% max, -40 to 85c 4 = 45/55% max, -40 to 85c, 50 mhz max package details part numbering guide 5.08 .200 max .46.08 .018.003 15.24.13 .600.005 max 13.0 .510 pin 7 gnd pin 14 +5 vdc pin 8 output max 0.91 .036 full size package pin 1 tri-state - nth n/c - nch nth 0 8 0 c 3 - 40.0000 nth - tri state nch - pin 1 n/c note a: c l includes probe and fixture capacitance *( ) indicates pin numbers for half-size package test circuit pin 1 input logic 1 or nc logic 0 or gnd pin 8 (5) output oscillation high impedance tri-state logic table (nth only) example pn: nth080c3 - 24.0001 required input levels on pin 1: logic 1 = 2.2v min logic 0 = 0.8v max frequency 3.3v supply package 0 = full size, thru-hole 9 = half size, thru-hole ma m power supply v m test point v dd out oscillator pin 14 (8) pin 8 (5) pin 1 (1) * pin 7 (4) gnd tri-state input (nth only) c l = 30 pf (note a) 21.0 .825 max 6.350.51 0.250.02 max (4) glass insulators 7.75 .305 saronix xtal osc standard marking format ** includes date code, frequency & model denotes pin 1 denotes pin 1 saronix 1.7 .067 6.0 .236 120 120 120 13.0 .510 max 7.62.20 .300.008 pin 5 output pin 8 v dd 1.5 .059 pin 1 tri-state - nth n/c - nch pin 4 gnd 7.62.20 .300.008 .46.08 .018.003 6.350.51 0.250.02 5.08 .200 max 0.91 .036 max max 13.0 .510 half size package standard marking format ** includes date code, frequency & model ** exact loaction of items may vary frequency range 3 = 1 to 4 mhz 6 = 4+ to 24 mhz 8 = 24+ to 70 mhz stability tolerance c = 100ppm b = 50ppm a = 25ppm ( 0 to +70 c only)
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